Researchers from Taiwan’s National Yang Ming Chiao Tung University (NYCU) and TSMC Corporate Research have built a 0.42 nm thick interface that removes a key bottleneck in next-generation transistors.

Solving the MoS2 Transistor Dilemma

For over a decade the industry has eyed atomically thin Molybdenum Disulfide (MoS2) as silicon’s successor. Its thinness promises smaller, faster, more energy-efficient transistors. Yet the "gate dielectric" problem has held back progress. When the insulating layer thins, the boundary with the semiconductor destabilises, spawning defects, gaps and electrical disorder that cripple performance. Researchers usually hunt for new insulators; the NYCU-TSMC team instead re-engineered the boundary itself.

The 0.42-Nanometre Innovation

In a Nature Electronics paper the team describes a layering process that smooths the atomic transition. They started with a monolayer MoS2 wafer, deposited an epitaxial aluminium film and oxidised it in place, creating an aluminium-oxide buffer only 0.42 nm thick. The buffer does two things: it provides a smooth foundation for a high-κ hafnium-oxide gate dielectric to grow uniformly, and it shields the semiconductor from unwanted electrical interactions. The resulting transistors show an equivalent oxide thickness of about one nanometre, low leakage current and almost no hysteresis, so the device responds predictably to signals.

Moving Toward Wafer-Scale Manufacturing

Crucially, the researchers grew the monolayer MoS2 with Chemical Vapour Deposition (CVD), the industry-standard method for coating large areas. Demonstrating the atomic interface on CVD-grown material pushes two-dimensional (2D) electronics toward real-world, wafer-scale production. The shift from "finding new materials" to "engineering interfaces" flips the design paradigm for future microchips.

What It Means for India

The breakthrough carries weight for India’s semiconductor mission and strategic autonomy.

  • Technological Benchmarking: India’s India Semiconductor Mission (ISM) must track the move from silicon to 2D materials like MoS2. Aligning R&D with interface-centric engineering will keep Indian labs from falling behind.
  • Supply Chain and Strategic Dependency: Taiwan’s dominance in high-end semiconductors deepens. India needs more than assembly and testing (OSAT) capabilities; it must nurture deep-tech research that can compete in next-generation material science.
  • Future-Proofing Digital Infrastructure: As India expands AI and high-performance computing, demand for energy-efficient chips will surge. Monitoring MoS2 transistor advances helps India plan hardware needs and protect digital sovereignty in a post-silicon era.

TSMC and National Yang-Ming Chiao-Tung University have engineered a 0.42 nm atomic-scale interface that eliminates the gate-dielectric bottleneck in MoS₂ transistors, a step that could bring two-dimensional (2D) chips to wafer-scale production. The breakthrough matters because it clears the last major hurdle preventing atomically thin materials from competing with silicon in speed, size and power efficiency.

The gate-dielectric problem that stalled 2D chips

For more than a decade MoS₂—a single-atom-thick semiconductor—has been touted as silicon’s successor. Its thinness promises faster switching and lower leakage. The promise vanished when manufacturers tried to shrink the insulating “gate dielectric” that controls the transistor. As that layer thinned, the boundary with the MoS₂ crystal filled with defects, creating electrical disorder and unpredictable behavior. Industry chased new insulators, but none formed a clean, uniform interface on an atom-thin channel.

An atomic buffer that smooths the transition

The team flipped the script: instead of hunting a better insulator, they re-engineered the interface. Starting with a CVD-grown monolayer of MoS₂, they deposited an epitaxial aluminium film and oxidised it in place, producing a 0.42 nm aluminium-oxide buffer. This ultra-thin layer does two things. First, it creates a smooth, chemically compatible surface for a high-κ hafnium-oxide gate dielectric to grow evenly. Second, it shields the MoS₂ channel from direct electrical interaction with the dielectric, suppressing defect formation that plagued earlier attempts.

The stack achieved an equivalent oxide thickness of roughly one nanometre while keeping leakage currents at the low end of the spectrum and eliminating hysteresis, the lag that distorts signal response. In short, the transistor behaved predictably across the full voltage range.

From laboratory flakes to wafer-scale promise

What sets this work apart is the use of CVD to grow the MoS₂ layer. CVD is the workhorse technique for depositing uniform films over large substrates, the same method used in today’s silicon fabs. Demonstrating the atomic interface on CVD-grown material shows the process can, in principle, scale beyond isolated chips to full wafers.

The researchers also employed standard epitaxial growth and oxidation steps that fit within existing fab toolkits. No exotic equipment or ultra-high-vacuum chambers beyond what a leading foundry already runs are required. This compatibility lowers the barrier for a foundry such as TSMC to integrate the method into its production lines.

Why the breakthrough matters beyond Taiwan

The achievement sends a clear signal to any nation building a future-proof semiconductor ecosystem. For countries like India, which are investing heavily in a domestic semiconductor mission, the work defines a new benchmark: success will increasingly depend on mastering interface engineering at the atomic level, not just on scaling silicon nodes.

  • Technology alignment – R&D programs that keep chasing bulk material improvements without addressing interface quality risk falling behind.
  • Supply-chain relevance – The process leans on aluminium, hafnium and standard oxidation steps, reinforcing Taiwan’s deep-tech advantage while highlighting the need for diversified material sources.